timing+delay

См. также в других словарях:

• Delay calculation — is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine …   Wikipedia

• Delay box — is a common slang term used in drag racing to describe an on board timer which is a Transmission Brake Delay Timer. A transbrake forces the race car to remain stationary at the starting line, in gear, regardless of how much engine power is… …   Wikipedia

• Delay-locked loop — In electronics, a delay locked loop (DLL) is a digital circuit similar to a phase locked loop (PLL), with the main difference being the absence of an internal voltage controlled oscillator. A DLL can be used to change the phase of a clock signal… …   Wikipedia

• Delay line memory — Computer memory types Volatile RAM DRAM (e.g., DDR SDRAM) SRAM In development T RAM Z RAM TTRAM Historical Delay line memory Selectron tube Williams tube …   Wikipedia

• Delay line oscillator — A delay line oscillator is a form of electronic oscillator that uses a delay line as its principal timing element. The circuit is set to oscillate by inverting the output of the delay line and feeding that signal back to the input of the delay… …   Wikipedia

• Delay of game — For Association football/soccer, see Timewasting. For the administrative decision to cease play and resume at a later time and/or day, see Delay (game). Delay of game is an action in a sports game in which a player or team deliberately stalls the …   Wikipedia

• Delay Insensitive Minterm Synthesis — Invented by David E. Muller, the DIMS (Delay Insensitive Minterm Synthesis) system[1] is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi Delay Insensitive delay model the generated designs… …   Wikipedia

• Delay-Locked Loop — Bei einer Delay Locked Loop (DLL) handelt es sich um eine elektronische Schaltung, die ähnlich wie eine Phasenregelschleife (PLL) aufgebaut ist. Der Hauptunterschied zur PLL ist das Fehlen des spannungsgesteuerten Oszillators, es wird nur das am… …   Deutsch Wikipedia

• Digital delay generator — A digital delay generator is a piece of electronic test equipment that provides precise delays for triggering, syncing, delaying and gating events. These generators are used in many types of experiments, controls and processes where electronic… …   Wikipedia

• Static timing analysis — is a method of computing the expected timing of a digital circuit without requiring simulation. High performance integrated circuits have traditionally been characterized by the clock frequency at which they operate.Gauging the ability of a… …   Wikipedia

• Constitutional growth delay — (CGD) is a term describing a temporary delay in the skeletal growth and thus height of a child with no other physical abnormalities causing the delay. Short stature may be the result of a growth pattern inherited from a parent (familial) or occur …   Wikipedia