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1 MICROPROCESSOR MEMORY
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2 I/O port
A channel through which data is transferred between a device and the microprocessor. The port appears to the microprocessor as one or more memory addresses that it can use to send or receive data.منفذ I/O -
3 input/output port
A channel through which data is transferred between a device and the microprocessor. The port appears to the microprocessor as one or more memory addresses that it can use to send or receive data.منفذ إدخال/إخراج -
4 CISC
"The implementation of complex instructions in a microprocessor design so that they can be invoked at the assembly language level. The instructions can be very powerful, allowing for complicated and flexible ways of calculating such elements as memory addresses. All this complexity, however, usually requires many clock cycles to execute each instruction." -
5 complex instruction set computing
"The implementation of complex instructions in a microprocessor design so that they can be invoked at the assembly language level. The instructions can be very powerful, allowing for complicated and flexible ways of calculating such elements as memory addresses. All this complexity, however, usually requires many clock cycles to execute each instruction."English-Arabic terms dictionary > complex instruction set computing
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6 ar-sa اللقب
"A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures." -
7 NMI
"A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures." -
8 nonmaskable interrupt
"A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures." -
9 page frame
"A block of contiguous physical memory that stores the contents of a virtual page. The size of the virtual page and page frame are usually identical. However, the size of a page frame depends on the microprocessor." -
10 Itanium
"An Intel microprocessor that uses explicitly parallel instruction set computing and 64-bit memory addressing. ""Itanium-based"" refers to systems or platforms that are based on the Itanium processor. ""Itanium2-based"" refers to systems or platforms that are based on the Itanium2 processor. ""Itanium architecture-based"" refers to systems or platforms that are based on the Itanium and Itanium2 processors." -
11 front side bus
The bus within a microprocessor that connects the CPU with main memory. It is used to communicate between the motherboard and other components in a computer system. -
12 FSB
The bus within a microprocessor that connects the CPU with main memory. It is used to communicate between the motherboard and other components in a computer system.
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