-
1 синхронизованный побайтно
синхронизованный побайтно
Положение в потоке битов считают байт-синхронизованным, когда это положение является целым кратным 8 битам от позиции первого бита в потоке битов. Бит, байт или элемент синтаксиса считают байт-синхронизованными, если позиция, на которой они появляются в потоке битов, является байт-синхронизованной (МСЭ-Т Н.264).
[ http://www.iks-media.ru/glossary/index.html?glossid=2400324]Тематики
- электросвязь, основные понятия
EN
Русско-английский словарь нормативно-технической терминологии > синхронизованный побайтно
-
2 выровненный сегмент байта переменной длины
выровненный сегмент байта переменной длины
(МСЭ-Т T.808).
[ http://www.iks-media.ru/glossary/index.html?glossid=2400324]Тематики
- электросвязь, основные понятия
EN
Русско-английский словарь нормативно-технической терминологии > выровненный сегмент байта переменной длины
-
3 байт-синхронизованный (о бите)
Information technology: byte-alignedУниверсальный русско-английский словарь > байт-синхронизованный (о бите)
-
4 байт-синхронизованный
Information technology: (о бите) byte-alignedУниверсальный русско-английский словарь > байт-синхронизованный
-
5 байт-синхронизованный
( о бите) byte-alignedRussian-English dictionary of telecommunications > байт-синхронизованный
См. также в других словарях:
Data structure alignment — is the way data is arranged and accessed in computer memory. It consists of two separate but related issues: data alignment and data structure padding. When a modern computer reads from or writes to a memory address, it will do this in word sized … Wikipedia
PCI configuration space — is the underlying way that the Conventional PCI, PCI X and PCI Express perform auto configuration of the cards inserted into their bus. Contents 1 Technical information 2 Standardized registers 3 Bus enumeration … Wikipedia
BSAVE (graphics image format) — A BSAVE Image (aka BSAVED Image ) as it is referenced in a graphics program is an image file format created usually by saving raw video memory to disk (sometimes but not always in a BASIC program using the BSAVE command).cite web|url = http://www … Wikipedia
Adler-32 — is a checksum algorithm which was invented by Mark Adler. Compared to a cyclic redundancy check of the same length it trades reliability for speed. Compared to its original form (Fletcher 16), Adler 32 is more reliable than Fletcher 16. However,… … Wikipedia
MOVAPD — In the x86 assembly programming language, MOVAPD is the name for a specific action performable by modern x86 processors with 2nd generation Streaming SIMD Extensions (SSE2). This action involves copying a pair of numbers to temporary space in the … Wikipedia
CPU cache — Cache memory redirects here. For the general use, see cache. A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the… … Wikipedia
CubeHash — CubeHash[1] is a cryptographic hash function submitted to the NIST hash function competition by Daniel J. Bernstein. Message blocks are XORed into the initial bits of a 128 byte state, which goes through an r round bijective transformation… … Wikipedia
NS320xx — The 320xx or NS32000 was a series of microprocessors from National Semiconductor ( NS , Natsemi ). They were likely the first 32 bit general purpose microprocessors on the market, but due to a number of factors never managed to become a major… … Wikipedia
Bit array — A bit array (or bitmap, in some cases) is an array data structure which compactly stores individual bits (boolean values). It implements a simple set data structure storing a subset of {1,2,..., n } and is effective at exploiting bit level… … Wikipedia
Bitmap index — A bitmap index is a special kind of database index.Bitmap indexes have traditionally been considered to work well for data such as gender, which has a small number of distinct values, e.g., male and female, but many occurrences of those values.… … Wikipedia
Sum addressed decoder — In CPU design, a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache… … Wikipedia