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21 NMI
"A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures." -
22 nonmaskable interrupt
"A hardware interrupt that bypasses and takes priority over interrupt requests generated by software and by the keyboard and other such devices. A nonmaskable interrupt cannot be overruled (masked) by another service request and is issued to the microprocessor only in disastrous circumstances, such as severe memory errors or impending power failures." -
23 page frame
"A block of contiguous physical memory that stores the contents of a virtual page. The size of the virtual page and page frame are usually identical. However, the size of a page frame depends on the microprocessor." -
24 smart card
"A plastic (credit card–sized or smaller) device with an embedded microprocessor and a small amount of storage that is used, with an access code, to enable certificate-based authentication. Smart cards securely store certificates, public and private keys, passwords, and other types of personal information." -
25 bound trap
"In programming, a problem in which a set of conditions exceeds a permitted range of values that causes the microprocessor to stop what it is doing and handle the situation in a separate routine." -
26 EC
"The general class of microcontrollers used to support OEM-specific implementation, mainly in mobile environments. The embedded controller performs complex low-level functions through a simple interface to the host microprocessor(s)."EC -
27 embedded controller
"The general class of microcontrollers used to support OEM-specific implementation, mainly in mobile environments. The embedded controller performs complex low-level functions through a simple interface to the host microprocessor(s)." -
28 Itanium
"An Intel microprocessor that uses explicitly parallel instruction set computing and 64-bit memory addressing. ""Itanium-based"" refers to systems or platforms that are based on the Itanium processor. ""Itanium2-based"" refers to systems or platforms that are based on the Itanium2 processor. ""Itanium architecture-based"" refers to systems or platforms that are based on the Itanium and Itanium2 processors." -
29 bitness
"A characteristic of a microprocessor's data stream (the distinction between 16-bit, 32-bit and 64-bit address spaces) and the potential differences in instantiation of components that this entails." -
30 front side bus
The bus within a microprocessor that connects the CPU with main memory. It is used to communicate between the motherboard and other components in a computer system. -
31 FSB
The bus within a microprocessor that connects the CPU with main memory. It is used to communicate between the motherboard and other components in a computer system. -
32 x86-based
"Pertaining to the combination of a 32-bit Windows operating system and a microprocessor that natively supports the 32-bit x86 instruction set. Examples include Intel Pentium 4, AMD Athlon and VIA C7 processors."
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